Get Accelerating Test, Validation and Debug of High Speed Serial PDF

By Yongquan Fan

ISBN-10: 9048193974

ISBN-13: 9789048193974

High-Speed Serial Interface (HSSI) units became frequent in communications, from the embedded to high-performance computing structures, and from on-chip to a large haul. checking out of HSSIs has been a not easy subject as a result of sign integrity concerns, lengthy try time and the necessity of pricy tools. Accelerating try, Validation and Debug of excessive pace Serial Interfaces presents cutting edge try out and debug methods and special directions on tips on how to arrive to useful try out of recent high-speed interfaces.

Accelerating try, Validation and Debug of excessive pace Serial Interfaces first proposes a brand new set of rules that allows us to accomplish receiver try greater than one thousand instances quicker. Then an under-sampling established transmitter try out scheme is gifted. The scheme can safely extract the transmitter jitter and end the complete transmitter try inside of 100ms, whereas the attempt often takes seconds. The booklet additionally offers and exterior loopback-based trying out scheme, the place and FPGA-based BER tester and a singular jitter injection process are proposed. those schemes should be utilized to validate, try out and debug HSSIs with facts expense as much as 12.5Gbps at a decrease try out expense than natural ATE recommendations. moreover, the e-book introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, compatible for comparing BER functionality below noise conditions.

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Extra resources for Accelerating Test, Validation and Debug of High Speed Serial Interfaces

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For HSSI receiver jitter tolerance testing, we need to stress the receiver with a pre-determined amount of jitter according to the related specification and then qualify whether the BER performance of the receiver is better than the specified BER level. Because the BER is usually defined at 10-12, it is too time consuming to conduct direct measurements in most cases. To accelerate the jitter tolerance qualification, we stress the receiver with controllable amounts of injected jitter. By varying the injected jitter in the input signal, we can make the receiver work at different higher BER levels, which are much less time-consuming to test.

Ideally, the data is always sampled in the mid-bit, sampling instance ts = UI/2 in Figure 2-11(a), where UI is the Unit Interval (period) of the signal. This is usually true if the jitter frequency is within the bandwidth of the CDR because the sampling clock is recovered from the data signal and the clock can track the inband jitter. However, for out-of-band jitter, the sampling clock cannot track the data any more and the jitter can cause bit errors. 24 2 Background Fig. 2-11. Jitter and BER in the receiver Figure 2-11(b) shows an example of the jitter profile.

Data transmission) go be9 low 10 errors out of 10 transmitted bits in many cases. , have to be optimized while satisfying the best trade-off between performances and complexity, which would further lengthen the simulation process. , emulation is proposed. As an alternative to simulation, emulation utilizes FPGAs to re-target all or part of a design. Many software tools and dedicated hardware [48], [49] have been developed with the aim of automating this retargeting process. In emulation, performance evaluation takes place in hardware, rather than in the virtual environment of a simulator.

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Accelerating Test, Validation and Debug of High Speed Serial Interfaces by Yongquan Fan

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